EDA News Monday November 17, 2003 From: EDACafe ÿÿ Previous Issues _____ Cadence _____ About This Issue Taxonomy recapitulates ontology Communication is the key _____ November 10 - 14, 2003 By Peggy Aycinena Read business product alliance news and analysis of weekly happenings _____ Sometimes things just fall into place in a quirky way. Like when you learn a bit of slang one day, just in time to be in the know the next day when somebody uses the phrase in a conversation and you're saved the embarrassment of asking what the heck we're all talking about. Terms like "sweet" or "sick" or "game" are ones best learned today, lest you not know tomorrow what the heck everybody's talking about. So it is in the lingo that surrounds technology. One day, some word or phrase is just a term; the next day, it's in common usage and everybody's banding it about around the coffee machine and you're trying to figure out (without asking outright) what the heck we're all talking about. That's why what you're about to read is going to prove useful. Things are happening in the world of phrases, lingo, slang, and lexicon, and you should be taking notice. The following disparate items - a couple of press releases and a letter from a reader - are all linked. If you read them, you'll be (closer to being) in the know and you'll avoid potential embarrassment next week or next month when somebody throws out something related to all of this. You won't be struggling (quite as much) to figure out what the heck they're all talking about. Sweet. Taxonomy Press Release I - Platform Based Design Taxonomy v1.0 VSIA (Virtual Socket Interface Alliance) announced the Platform Based Design (PBD) Taxonomy 1.0 has entered Member Review. This is the first document brought to Member Review from the PBD Development Working Group (DWG), created in June 2002. The PBD taxonomy document defines appropriate terminology for the fundamental concepts in platform-based design and classifies platforms with respect to their levels of complexity and three basic design approaches. The overall goal of the PBD DWG is to allow both the platform-architecture developer and the design teams creating platform-derivative products to evaluate and select platform architectures and differentiating Virtual Components that are best for their application. PBD Taxonomy 1.0 will be in Member Review through December 12, 2003 and VSIA members are encouraged to download, review and comment on the document. The PBD Taxonomy provides definitions of common terms and concepts used by platform developers and users. This taxonomy classifies platforms according to their complexity, as well as three platform design styles: - Bottom-up (or technology-driven) (e.g., an FPGA plus a processor core) - Middle-out (or architecture-driven) (e.g., a processor core plus an on-chip bus) - Top-down (or application-driven) such as a domain-specific family of SoCs (e.g. MXC, Nexperia, or OMAP) The PBD Taxonomy also introduces the notion that platform-based products are designed in two phases. This leads to two basic design-team interfaces for platform-based design: "Platform Interface" between the basic component building blocks such as buses and Virtual Components (also known as IP) and the "Architecture Platform" - and the "Derivative Interface" between the "Architecture Platform" and its "Application Derivatives" Additionally, the Interface definitions set the stage for the next and critical contribution from the PBD DWG: Deliverables from the platform architecture developer to the platform derivative developer. Per Bob Altizer, PBD Chair and President, BASYS Consulting: "In order to define platform classes and provide a common language, VSIA brought together some of the best engineering minds from key companies in the industry including Alcatel, ARM, Cadence, Infineon, Nokia, ST Microelectronics, Synopsys and Toshiba, among others. The result of the past year's work is a sound foundation upon which to develop vital specifications and standards." Press Release II - Hardware-dependent Software Taxonomy v1.0 VSIA released Hardware-dependent Software Taxonomy Version 1.0 (HdS 1 1.0). This is the first document released from the HdS Development Working Group (DWG), which was created September 2001. The purpose of this document is to define and put into perspective common terms important in the HdS context - thereby improving the relationship and communications between SoC hardware and embedded software engineers. The longer-term goal of the HdS DWG is to improve intra-company and inter-company software "virtual component" re-use by specifying an "HdS API." The HdS Taxonomy defines key silicon-hardware terms and concepts for an embedded-software-engineer audience and similarly defines key embedded-software terms and concepts for hardware-and-platform-development engineers. It also establishes an HdS Taxonomy focused on HdS product development and support in terms of life cycle; hardware and embedded-software-architecture; and platform-design axes. This Hardware-dependent-Software Taxonomy is intended for and includes the contributions of SoC-IP providers, system integrators, EDA tool providers, and OS providers. Per Frank Pospiech of Alcatel and Chair of the VSIA HdS DWG: "Companies such as ARM, Nokia, Toshiba, Alcatel, Mentor Graphics, Cadence and Beach Solutions have all helped create this taxonomy document, highlighting the fact that there is an industry-wide interest in solving this issue. The release of this taxonomy document is the first step to creating the HdS-API standard, which will help drive SoC productivity by lessening the design gap between hardware and software layers." Ontology A Letter to the Editor - Ontologies for Electronic Systems The complexities in electronic systems design are creating technical challenges not only for the EDA tools and methodologies, but also for the information infrastructure required to support the entire design chain from concept to finished product. The infrastructure requirements also extend into the product's lifecycle support. Most companies today are relying on a plethora of IT products to help manage the design, development, testing and support activities related to products. Unfortunately, it's not uncommon to have duplicate data, out of date data, wrongly classified data, and overall general chaos due to the absence of uniform processes for data handling. The problems are particularly intense as project management attempts to track design flow, and crucial library and silicon IP data. Although many companies deploy piecemeal solutions to address these problems, very little is being done to understand how such solutions contribute towards the overall improvements needed to facilitate IP reuse, shorten the design cycle, or meet other quality goals. Companies need to realize that improvements in quality come about as a consequence of effective sharing and reuse of knowledge across its workforce. Such sharing and reuse can be facilitated by integrating the various infrastructure solutions through development of metadata standards, ontologies and ontology reuse. An ontology is a vocabulary of entities, classes, properties, functions and their relationships. Ontologies are meant to provide an understanding of the static domain knowledge that facilitates knowledge sharing and reuse. Among the ontologies identified by Fensel in his 2001 article, "Ontologies: A Silver Bullet for Knowledge Management and Electronic Commerce" are: 1) Domain ontologies, representing a target domain, such as engineering, medicine, etc. 2) Generic or Common Sense ontologies, capturing general knowledge about time, space, events, etc. 3) Metadata ontologies, describing the content of information sources. Metadata describes data - it is definitional data that provides information about other data managed within an application. For example, metadata could document data about: - Attributes: clocks, signals, size, signal type - Data structures: timing (rise time, fall time, etc.) and test requirements - Data: where it is located, how it is associated :Being able to describe data is essential for data interchange. Metadata as part of a dataset allows the dataset to be "self-describing", so that an application can adjust its handling of that dataset according to the values of the metadata. Of course, users must adopt standard conventions within their own systems as to what constitutes metadata. No matter how metadata is defined, however, self-description is the critical feature in transporting data between different tools, tools that have different models or conventions for handling data. The metadata, thus, provides a guide for converting the data between the different conventions. Work has been done on Generic ontologies (cyc, SUO, GO, etc.), Metadata ontologies (Dublin Core, LOM, etc.) and Domain ontologies. The recently announced SPIRIT consortium has said that it will work toward developing a standard IP metadata ontology that aims to capture all the IP design, test and integration information and views needed to transfer and exchange IP between companies, so IP users don't have to waste time trying to characterize IP to fit it into their design flows. Additionally, many generic ontologies have been contributed to the public domain at the daml.org website and there are many other new ones being published. However, when it comes to domain ontologies dealing with electronics and the SoC design value chain, I have only been able to locate a handful. ScaffoldTech specializes in helping organizations to develop ontologies and applications based on the use of such ontologies. We believe that it is to the benefit of the whole community to develop ontologies that can be re-used. In the spirit of the open source movement, ScaffoldTech is setting up a community forum where experts can discuss and arrive at domain ontologies for electronic systems. The forum site will be available by early December: [ ] Bellave Jayaram ScaffoldTech (Editor's Note: Originally, it was phylogeny that recapitulated ontogeny.) Industry News - Tools and IP Accelerated Technology, the Embedded Systems Division of Mentor Graphics, announced the availability of the Nucleus NET embedded TCP/IP protocol stack for networking developers using the OSEK standard, an industry operating system specification for automotive systems. The company says that the Nucleus NET protocol stack allows OSEK users to develop an automotive electronics application that can communicate outside the vehicle. Per the Press Release: "An OSEK device, such as the anti-lock braking system of an automobile, might need to communicate with the automobile's telematics system to display status information to the driver. Another scenario is for the automotive powertrain system to communicate with a diagnostics tool, often a handheld computer or a personal digital assistant (PDA). In these cases, it is preferable to communicate over Ethernet and TCP/IP rather than those specifications defined by OSEK for communications between control units." "Cost and availability are two of the primary reasons to communicate over Ethernet and TCP/IP. The cost of Ethernet hardware and TCP/IP software is low when compared to competitive solutions, reducing further development costs since it is unnecessary to develop custom communications software for the external devices that need to communicate with the control units. Rather, commercial off-the-shelf (COTS) software and hardware can be used for the communications." "Accelerated Technology saw the demand for a robust TCP/IP protocol stack compatible with the OSEK specification and worked with a car manufacturer, building a racecar prototype, to bring this product to market. The Nucleus NET TCP/IP protocol stack was modified so it could be built in static mode, so that the software's resources were allocated upon initialization rather than allocated as needed. This results in a TCP/IP stack that is more deterministic, which is a critical requirement for most of the embedded systems in which OSEK is used." Agilent Technologies Inc. announced an addition to Agilent's RF Design Environment (RFDE) that includes full-wave EM modeling capability for RF and mixed-signal design from within Cadence Design System's Virtuoso custom-design platform. Per the Press Release: "Today, physical-level analysis of ICs is typically performed with resistor-capacitor extraction technology, which provides rules-based modeling of parasitics for an entire IC. RFDE Momentum allows Cadence users to perform more accurate full-wave EM modeling on select Virtuoso cells, as well as physical verification of critical passive nets. These critical functions bring an extremely high level of confidence to the RF mixed-signal IC design process." Altium Ltd. announced version 10.0 of its TASKING 68K embedded software development toolset. In the new release, the toolset has been enhanced to support ColdFire microprocessors as well as new Motorola 68K & CPU32 derivatives (including the DragonBall 68xx328 series). Other major enhancements include a more intuitive Embedded Development Environment (EDE) and a next-generation version of the CrossView Pro debugger. Per the Press Release: "Extensively redesigned interfaces for both the EDE and the next-generation CrossView Pro debugger in v10.0 results in a more intuitive environment and enhanced ease of use for developers. The re-arranged menu structures, improved dialogs, and new context-sensitive help features make the toolset easy to learn and use." Analog Design Automation, Inc. (ADA) released Creative Genius v2.1 and IP Explorer v2.1, high-capacity optimization tools for designers of analog, mixed-signal and custom integrated circuits (ICs). The company says the new versions are 5x to 10x faster than the previous versions, due to "improved optimization algorithms and more streamlined processes for simulating across environmental and manufacturing process corners. Creative Genius v2.1 enables designers to optimize up to 200 devices across 60 environmental and manufacturing variations, with 30+ performance goals. IP Explorer v2.1 is the only analog/mixed-signal analysis tool that enables designers to work interactively with vast amounts of numerical information, dynamically steer the optimization process, explore trade-offs, and select the circuit that best meets their demanding specifications." The Press Release also included an endorsement from Fyre Storm, which said its designers reduced time by 30 percent and met their design schedules using Genius v2.1. Cadence Design Systems, Inc. announced that Cadence Engineering Services enabled Zoran Microelectronics LTD. to meet its targets for launching the SupraTV 150 SoC, a chipset for set-top box and digital television markets. The companies say that collaboration through the Cadence Virtual Integrated CAD (VCAD) service model allowed the companies' engineers to work remotely on design challenges, and that joint Cadence and Zoran teams implemented and managed Zoran's design environment from netlist to GDSII, all the way to ongoing operations and enhancement support. Cadence Design Systems, Inc. announced that a component of the Cadence Encounter digital IC design platform, the NanoRoute router, has taped out its 100th IC design since its first tape-out 18 months ago. Per the Press Release: "NanoRoute has been used on leading-edge microprocessor, networking, graphics, telecommunications and other designs in both ASIC/ASSP and COT methodologies." Mentor Graphics Corp. announced the extension of the integration of their Expedition PCB design solution with the Cadence Allegro PCB layout system. The company says that integration with the Allegro libraries and database will allow customers to use Mentor's Expedition Series advanced layout and routing capabilities with their Allegro flows, including libraries and design data. Henry Potts, Vice President and General Manager of the Systems Design Division at Mentor, is quoted in the Press Release: "PCB is a strategic part of Mentor Graphics' business and we are continuing to invest heavily in R&D and technology acquisitions to keep ahead of rapidly advancing PCB and IC/FPGA technology. We are now happy to be able to support customers using mixed environments so they can take advantage Expedition's advanced technology." 0-In Design Automation announced the availability of an enhanced assertion compiler, which is one component of the 0-In Assertion-Based Verification (ABV) Suite. The company says the suite "builds on the standardization work of IEEE and Accellera to provide the industry's most comprehensive interoperability strategy for assertions and formal verification." The 0-In assertion compiler permits multi-way interoperability between various assertion formats and verification tools. It accepts assertions in the following formats: Accellera's Property Specification Language (PSL), Accellera's SystemVerilog Assertions (SVA), IEEE-1364 Verilog, Accellera's Open Verification Library (OVL), the 0-In CheckerWare library (CW). The 0-In compiler reads in assertions in any of these five formats and synthesizes HDL assertions in a format that can be used in any third-party simulator, formal verification tool, hardware-assisted verification box or even FPGA prototyping system. This allows assertions written in PSL or SVA to be usable by tools that do not directly accept these formats. Sequence Design announced that Renesas Technology Corp. has standardized on its Columbus-AMS RLC parasitic extractor for 90-nanometer designs. Columbus-AMS is a 3-D, RLC extractor for mixed-signal, analog, memory, and full-custom digital designs, and is a component of Sequence's ExtractionStage suite of tools. Renesas Technology was established in 2003 as a joint venture between Hitachi, Ltd. and Mitsubishi Electric Corp. Synopsys, Inc. announced that its DesignWare USB 2.0 Multiport Host and Physical Layer (PHY) are the first host IP building blocks to achieve Hi-Speed certification from the USB Implementers Forum (USB-IF). The company says that its USB IP has also passed the Microsoft Windows Hardware Qualification Lab Hardware Compatibility Tests (WHQL HCT) on Windows XP and 2000 for compatibility with standard drivers. Per the Press Release: "The Hi-Speed logo tells designers that the IP they are deploying is interoperable and compliant to the specification, which enables throughput of up to 480 Mbps, 40 times faster than the original USB specification (12 Mbps). Certification is critical if USB products are to successfully interoperate with other USB devices. The WHQL certification indicates plug and play interoperability and compatibility with Windows XP and 2000 operating systems." SpiraTech announced the availability of its Cohesive product line, which the company describes as the first family of products that provides an ESL to RTL flow through the use of full spectrum abstraction adaptation. Cohesive includes an ESL and RTL debugger, a system-level performance profiler, and a multi-level protocol checker, as well as visualization of the relationship between system-level, transaction-level and wire-level activity. I spoke with Simon Calder, Vice President of Sales and Marketing at SpiraTech, about the announcement. Here are Calder's comments: "The migration from RTL to ESL has begun. It's not at an advanced stage yet, but it's gaining momentum. There are now several large power users around the world, and we believe mainstream acceptance will rapidly accelerate. There are 3 reasons for this. First is silicon quality. Second is design productivity - people think they can build huge simulation farms in combination with billions of automatically generated test vectors, [but that's becoming untenable]. Design productivity on projects with 30 million gates or more is impacting schedules as RTL has become only incrementally more productive. People [are responding] by throwing more engineers on the project. Finally, increasing costs are translating into fewer projects, [fewer design starts]." "The downturn has clearly left some companies with excess engineering capacity. They have three choices in how to cope with this. They can have large lay-offs, they can re-deploy engineers on to fewer, larger, RTL based projects or they can use the spare resource to make the one time up front effort to shift their design paradigm to the next level of abstraction. No prizes for guessing which response gives the most long term benefits. SpiraTech's products considerably reduce the up front effort of adopting ESL." "When I was working for AMCC, at one stage we had 20 or 30 projects, all with full teams of designers and implementers pushing the back-end resources. Today, they've cut the number of projects by half or more, but they've only cut [their engineering staff] by a quarter. People feel they can keep going [in touch economic times] by putting more engineers on less projects." "[All of this is pushing the need for ESL design.] ESL converts will tell you that there's no reason why, using ESL technology, a platform capable of developing software should not be available upon the immediate completion of the architecture. There are time-to-revenue savings here [of upwards] of 18 months to 2 years. I say to those [who are resisting the move] - if you don't do it [ adopt ESL], your competitors will. And EDA vendors who don't make the change? They'll begin to see that their customers, the semiconductor vendors, are [under the gun] to provide system-accurate models of SoCs [early on in the project] to their own customers. Today, a lot of EDA vendors are betting the ranch promising things and tools that no longer work. But I know there are a lot of disgruntled customers out there who are beginning to insist on better tools for evaluation and software implementation." "A lot of customers today are now convinced of the beauty of ESL. They know there's a pretty straightforward communication from the gate level up to the RTL. What they don't know is how to get from ESL down to the RTL. ESL needs to transit [across] multiple levels of abstraction - instruction accurate, performance accurate, and slot accurate models. We strongly believe that what we're providing is the first true link between ESL and RTL, and that unless there's a link between these two levels, ESL is never going to be viable." "Right now, our customers see SystemVerilog as a new Verilog, not as a system language. SystemVerilog wants to look back to the old RTL abstraction level. From our perspective, SystemC is the language of ESL - our models are in SystemC. But the logic of adopting SystemC for ESL is overpowering. SystemC is a quantum leap in terms of abstraction. In the U.S., however, there are still [lots of vendors] going on in proprietary C++ environments. They should look at a leading indicator - the fact that Venture Capital dollars are going into companies that are starting to synthesis straight out of SystemC. The VCs know that the major semiconductor companies want to give their customers an environment for building a system with more than one vendor, and SystemC provides a standardization of that mess. There's no way a proprietary C++ environment [will suffice]." "There are lots of tools today - many System C-based - but we would argue that they are just co-existing, not co-habitating. There are many products making offers that are meaningless with respect to system performance. What we're talking about is enabling relationships between models at all levels of abstraction. It's a complex problem [addressing] new levels of abstraction, not just new languages." Coming soon to a theater near you DATE 2004 - Ask anybody and they'll tell you that the Design, Automation and Test in Europe conference and exhibition is a must-attend event for both Europeans and many in the international community involved in electronic system design and test. This past spring, DATE was held in Munich, Germany. This next year it will be in Paris, France, running from February 14th to the 20th at CNIT, Paris La Defense. The General Chair of the upcoming conference is Joan Figueras, Professor at the Universitat Politecnica de Catalunya. He was in his office in Barcelona, Spain, when we spoke by phone last week. Prof. Figueras said, "I'm confident that we'll have over a thousand people attending DATE in February. And if the economy keeps going up, we hope that the companies will send even more delegates. Right now, we are very optimistic about the numbers." "We are very happy because we've increased significantly the number of proposals with respect to last year - an increase of 37 percent - and we appear to have [as many if not more] than other EDA conferences this year. We've added an additional track just to accommodate the extra papers that have been submitted. Of course, the fact that DATE is in Paris in 2004 might have something to do with all of this [interest]." "The U.S. is the country that has submitted the most papers to us, then Asia. Japan has a high participation, but also Malaysia and South East Asia. Also, China's submissions have increased significantly since the Chinese first started looking at international conferences. Overall, we expect an extensive international participation in February." "DATE evolved from an agreement between two previous conferences - ED&T [Electronic Design & Test] and EuroDAC, which was always in Munich, Germany. The results of the combining of the two was DATE, which is an excellent conference because it combines the industrial nature of EuroDAC with the high-level academic emphasis [associated] with ED&TC." "At DATE 2004, I'll be in charge of chairing the opening ceremony, where various awards are given to people - the IEEE awards, awards from other societies, best paper awards, and design awards. Some of these awards are for old people - the lifetime achievement awards. But some awards are for young people, and those awards are also important because they give motivation [to young researchers]. For instance, we have the best PhD [thesis] award and the best design award [being given] to young engineers. These awards create history for young people. People who receive these awards see that quality is rewarded, so they will be even more intense in their research and more competitive." "The keynote address will be given by Greg Spirakis, who is a Vice President at Intel. I know him personally as I spent a sabbatical year in the U.S. at Intel in Santa Clara. I think Greg is an excellent speaker, very bright, and able to answer questions in a very precise way. That is why I invited him to give the opening keynote. We [actually] have three keynotes - one at the opening ceremony, one on the special day focused on low-power design, and a third keynote address discussing multi-media design. Greg is an American, the other two speakers are European - an appropriate balance for the conference." Newsmakers Accellera announced the formation of a new Accellera technical subcommittee for the standardization of custom design kit data, the Accellera OpenKit (OK) Initiative. Per the Press Release: "The establishment of standard formats for custom design data will save a significant amount of engineering time currently spent in integrating tools with design kits, as well as simplify the use of multiple tools, flows and different IC processes. Design kits provide information required by EDA tools during the simulation, implementation and verification steps of IC design. This information includes process design rules, device models, schematic symbols, and parameterized cells used for custom layout. To date, standards are largely nonexistent in the area of design kits. Nomenclature, use models, interfaces, quality thresholds, and delivery structures and mechanisms can vary widely depending on the selection of tools, library or IP and the targeted foundry requirements." Open Core Protocol International Partnership announced the availability of an OCP Compliant IP Library listing through the group's Web site, which should facilitate finding OCP compliant third party IP. Companies featuring products include: 3rdeye Technology, Advanced Architectures, Amphion Semiconductor, CAST, Denali Software, eInfochips, HDL Design House, Imagination Technologies, MIPS Technologies, Mentor Graphics, Prosilog, Sonics Inc. and Synergetic Computing Systems. The initial list currently contains over 200 pieces of IP listed. Also included is an OCP Compliant EDA products section with contributions from additional companies including: Beach Solutions, Cadence, NoBug, Prosilog, TNI-Valiosys, Verisity and YogiTech. In the category of ... They wouldn't say it if it wasn't true The Semiconductor Industry Association (SIA) made a splash in the business and technology publications this past week when it released its annual forecast for 2003-2006, which included a robust growth forecast for 2004. SIA says global sales of semiconductors in 2003 will increase by 15.8 percent to $163 billion, and continue to increase in 2004 by 19.4 percent to $194.6 billion. John Daane, Chairman, President and CEO of Altera Corp., presented the forecast at SIA's annual award dinner and is quoted in the subsequent Press Release: "We are on an accelerated growth path and this is great news. Growth will be broad based across all markets. We are facing an inflection point in our industry where chip development costs are rapidly increasing with each new process node. We believe that this is going to result in some fundamental changes in our industry. Now, more than ever, semiconductor manufacturers are forced to closely evaluate the return on investment of each chip produced. New opportunities lie in programmable architectures such as microprocessors, microcontrollers, DSPs and programmable logic, which can be leveraged across many customers and many markets. Cost and flexibility will be the keywords going forward." (Not a particularly surprising technology endorsement from an FPGA guy, but heartening nonetheless.) Meanwhile, SIA says American markets will grow 1.9 percent in 2003 and 17.7 percent in 2004, European markets should expect 17.3 percent growth in 2003 and 14.7 percent in 2004, Japanese markets will see 24.3 percent growth in 2003 and 17.9 percent in 2004, and the Asia Pacific market will grow by 18.6 percent in 2003 and 23.4 percent in 2004. SIA also looked into its crystal ball and read out predictions for various product categories including discrete components, optoelectronics, analog, MOS logic, microprocessors, DSPs, etc. All categories apparently show promise, but none so much as the Flash memory product classification. SIA says this one's going to be the real winner - a 42.7 percent growth expected in 2003, followed by 36.4 percent growth in 2004. Press Release Taxonimy By way of letting off a little steam, here's an admittedly incomplete taxonomy of overused stuff that often crops up in press releases: Comprehensive -What does "comprehensive" really mean? Could we just use the term "complete?" Robust - This is an authentic engineering adjective that's died a thousand deaths with so much overuse in press releases. Innovative - Who's going to crow about something that's "good, but not terribly new or creative?" Of course it's innovative, so could we just say, "This one's really hot!" or maybe, "Check this one out! It's a real rip-snorter!" - just to spice things up a little. Value add - Considering what you're charging, let's hope you're adding value. Industry leading - According to whom? Is this a scientifically verifiable claim? Leading edge - Ditto. De facto standard - Ditto, again. Enables - How about "assists" or "makes it possible to :" Success - Who ever advertises a failure? Patented - Do you mean, 'Don't even think about touching it.' Or do you mean, 'We've got it and you don't.' Solution - Could we please just call them tools or products or suites? Does everything have to be a "solution?" Next generation - Does this mean 90 nanometers or simply, "This isn't your father's model checker." Accelerates delivery - How about: "It helps to get products out faster." Highly complex - When was the last time you saw a design, die, package, or board that wasn't highly complex? Traction - Isn't this a term that belongs to the folks at John Deere? Service the needs - How about the prosaic, but honest: "We're out here to help the guys who need help." Isn't that the language of real people, people like engineers? Synergistic - Arrrgh! Paradigm - No comment. Finally, the one uber-phrase that seems to have finally died on the vine: Low hanging fruit --Peggy Aycinena is a Contributing Editor and can be reached by clicking here . You are subscribed as: [dolinsky@gsu.by]. CafeNews is a service for EDA professionals. EDACafe respects your online time and Internet privacy. To change your subscription details, including format and frequency, or to unsubscribe, please click here or visit http://www10.edacafe.com/nl/newsletter_subscribe.php. If you have questions about EDACafe services, please send email to edaadmin@ibsystems.com . Copyright c 2003, Internet Business Systems, Inc. All rights reserved.